1. Field of the Invention
The present invention relates to a fabrication method for an interconnect structure of an integrated circuit. More particularly, the present invention relates to a fabrication method for an inter-metal dielectric layer.
2. Description of the Related Art
The multilevel interconnect structure has been widely employed to accommodate the continuing demand in the integrated circuit manufacturing to produce a more powerful and highly integrated device in a smaller area. In such an interconnect structure, a conductive material, for example, a metal line, on one interconnect level is electrically insulated from a patterned conductive material on the other interconnect level by an inter-metal dielectric (IMD) layer. Connections between the conductive material on the various levels of the interconnect are made by forming an opening, which is often referred as a via, in the inter-metal dielectric layer to expose a certain portion of the underlying metal line. A conductive contact, also known as a via plug, is then formed in the via to connect the underlying metal line with the overlying metal line. The via and the via plug thus serve to enable an electrical contact between the conductive materials at various interconnect levels.
According to the conventional fabrication method for an interconnect structure by means of a dual damascene manufacturing process, a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer are sequentially formed on a substrate to serve as the inter-metal dielectric layer. Photolithography and etching are further conducted to form a trench line in the second silicon oxide layer. During the definition of the trench line, the silicon nitride layer serves as an etch stop layer, preventing an over-etch from occurring during the formation of the trench line. Photolithography and etching are further conducted to define the silicon nitride layer and the first silicon oxide layer, thereby to form a via under the trench line. A copper layer is then subsequently formed to fill the trench line and the via. These processing steps are then repeated to form the next level of the interconnect.
A consequence of having multiple layers of the patterned conductive material separated by an insulating layer is the formation of an undesired parasitic capacitance. The presence of parasitic capacitance in microelectronic devices contributes to adverse effects such as RC delay, power dissipation and cross-talk. The silicon nitride layer, which is a part of the inter-metal dielectric layer and also plays a role as an etch stop during the formation of the trench line, has a dielectric constant (k) of about 7, which significantly increases the inter-metal dielectric (IMD) capacitance.